1. Field of the Invention
The present invention relates to a thin film transistor suitable for use as a switching element, and more specifically to a thin film transistor of a small off current or of a high on/off current ratio.
2. Description of the Prior Art
A prior-art thin film transistor is well known as shown in FIG. 1A, in which only the basic transistor structure is diagrammatically depicted. In the drawing, the transistor includes a channel forming region 1, source and drain regions 2 and 3, a gate insulating film 4, and a gate electrode 5.
The channel forming region 1 is a semiconductor thin film formed of polysilicon or amorphous silicon, for instance having neither n-type nor p-type impurity doped intentionally or having a sufficiently low n-type or p-type impurity concentration. The source and drain regions 2 and 3 are a semiconductor thin film formed of polysilicon or amorphous silicon, for instance having a sufficiently high n-type or p-type impurity concentration, respectively as compared with that of the channel forming region, and arranged at first and second different positions adjoining to the channel forming region 1, respectively. Further, the gate electrode 5 is formed over a principal plane 1a of the channel forming region 1 and between the source region 2 and the drain region 3, via the gate insulating film 4 formed of silicon oxide, for instance.
In the prior-art thin film transistor constructed as described above, when a positive control voltage is applied by a control voltage supply 8 to the gate electrode 5 with the source region 2 as zero voltage level, as shown in FIG. 1A-1, under the condition that a positive voltage is applied to the drain region 3 by another voltage supply 6 via a load 7, since an n-type channel layer 10 is formed within the channel forming region 1 and under the gate electrode 5 so as to expand from the gate insulating film 4 in the direction opposite to the gate electrode 5 and extend between the source and drain regions 2 and 3, the range between the source and drain regions 2 and 3 is turned on, so that current is supplied from the voltage supply 6 to the load 7.
Under these conditions, when a negative control voltage is applied by the control voltage supply 8 to the gate electrode 5 with the source region 2 as zero voltage level, as shown in FIG. 1A-2, since a p-type channel layer 11 is formed within the channel forming region 1 and under the gate electrode 5 so as to expand from the gate insulating film 4 in the direction opposite to the gate electrode 5 and extend between the source and drain regions 2 and 3, a backward pn junction 12 is formed between the n-type drain region 3 and the p-type channel layer 11, so that the range between the source and drain regions 2 and 3 is turned off and therefore current is not supplied from the voltage supply 6 to the load 7.
Accordingly, the prior-art thin film transistor shown in FIG. 1A can be preferably used as a switching element.
Further, another prior-art thin film transistor has been proposed by the same applicant as shown in FIG. 1B. In the drawing, this prior-art thin film transistor shown in FIG. 1B is basically the same in structure as the previous prior-art transistor shown in FIG. 1A except that an offset region 20 of a semiconductor thin film formed of polysilicon or amorphous silicon, for instance having an n-type impurity concentration lower than that of the drain region 3 is interposed between the channel forming region 1 and the drain region 3. Therefore, the same reference numerals have been retained for similar elements which have the same functions, without repeating any detailed description of them.
In this prior-art thin film transistor constructed as described above, when a positive control voltage is applied by a control voltage supply 8 to the gate electrode 5 with the source region 2 as zero voltage level, as shown in FIG. 1B-1, under the condition that a positive voltage is applied to the drain region 3 by a voltage supply 6 via a load 7, since an n-type channel layer 10 is formed within the channel forming region 1 and under the gate electrode 5 so as to expand from the gate insulating film 4 in the direction opposite to the gate electrode 5 and extend between the source region 2 and the offset region 20 in the same way as with the case of the prior-art transistor shown in FIG. 1A, a range between the source region 2 and the drain region 3 is turned on via the offset region 20, so that current is supplied from the voltage supply 6 to the load 7.
Further, under these conditions, when a negative control voltage is applied by the control voltage supply 8 to the gate electrode 5 with the source region 2 as zero voltage level, as shown in FIG. 1B-2, since a p-type channel layer 11 is formed within the channel forming region 1 and under the gate electrode 5 so as to expand from the gate insulating film 4 in the direction opposite to the gate electrode 5 and extend between the source region 2 and the offset region 20 in the same way as with the case of the prior-art transistor shown in FIG. 1A, a backward pn junction 13 is formed between the n-type offset region 20 and the p-type channel layer 11, so that the range between the source and drain regions 2 and 3 is turned off and therefore current is not supplied from the voltage supply to the load 7.
Accordingly, the prior-art thin film transistor shown in FIG. 1B can be preferably used as a switching element in the same way as with the case of the prior-art transistor shown in FIG. 1A.
In the case of the prior-art thin film transistor shown in FIG. 1A, as already explained, the p-type channel layer 11 is formed within the channel forming region 1 when the transistor is turned from on (as shown in FIG. 1A-1) to off (as shown in FIG. 1A-2). In this turn-off state, however, a depletion layer is formed at the pn junction 12 between the n-type drain region 3 and the p-type channel layer 11 in such a way as to extend toward both the drain region 3 and the channel layer 11, respectively. In this case, since the drain region 3 is formed of a semiconductor having a relatively high n-type impurity atom concentration, the width of the depletion layer extending toward the drain region is relatively narrow. That is, since the depletion layer existing at this pn junction 12 is relatively narrow in width, when the transistor is kept turned off, a relatively high electric field is generated at the depletion layer of the pn junction 12 between the drain region 3 and the channel layer 11, so that there exists a problem in that a relatively large leakage current flows from the drain region 3 to the source region 2 through traps existing at the depletion layer extending between the drain region 3 and the channel layer 11 in the transistor turn-off state.
In the case of the prior-art thin film transistor shown in FIG. 1B, as already explained, a p-type channel layer 11 is formed within the channel forming region 1 when the transistor is turned from on (as shown in FIG. 1B-1) to off (as shown in FIG. 1B-2). In this state, in the same way as in the transistor as shown in FIG. 1A, a depletion layer is formed at the pn junction 13 between the n-type offset region 20 and the p-type channel layer 11 in such a way as to extend toward both the offset region 20 and the channel layer 11, respectively. In this transistor, since the offset region 20 is formed of semiconductor having a relatively low n-type impurity concentration, the width of the depletion layer extending toward the offset region 20 is relatively wide. That is, since the depletion layer existing at the pn junction 13 is relatively wide in width, when the transistor is kept turned off, a relatively low electric field is generated at the depletion layer at the pn junction 13 between the offset region 20 and the channel layer 11, so that a relatively low leakage current flows from the drain region 3 to the source region 2 through defects existing (if any) at both the depletion layers extending toward the offset range 3 and the channel layer 11 in the transistor turn-off state. That is, in the transistor shown in FIG. 1B, it is possible to markedly reduce the leakage current flowing from the drain region 3 to the source region 2 when the transistor is kept turned off.
In the case of the prior-art thin film transistor shown in FIG. 1B, however, when the offset region 20 is formed to such a low concentration that the off current can be sufficiently suppressed, since the resistance of this region 20 becomes higher than that of the channel 10 or the drain region 3 formed in the active region 1, there exists a problem in that the on current is extremely reduced, since an offset region 20 must be formed between the channel forming region 1 and the drain region 3 by a semiconductor thin film having an n-type relatively low impurity concentration as compared with that of the drain region 3, there exists a problem in that the manufacturing process is complicated to form the offset region 20 and therefore the manufacturing cost is high.